</a>led" title="led">led" title="led">led interconnects. The Serializer is offered in a 32-pin LLP package and the Deserializer is offered in a 48-pin LLP package.
DS90UB913Q/DS90UB914Q主要特性:
● 10 MHz to 100 MHz input pixel clock support
● Single differential pair interconnect
● Programmable data payload:
— 10 bit payload up to 100Mhz
— 12 bit payload up to 75MHz
● Continuous Low Latency Bidirectional control interface channel with I2C support@400kHz
● 2:1 Multiplexer to choose between two input imagers
● Embedded clock with DC Balanced coding to support ACcoupled interconnects
● Capable of driving up to 25 meters shielded twisted-pair
● 4 dedicated General Purpose Input (GPI)/ Output (GPO)
● LOCK output reporting pin and AT-SPEED BIST diagnosis feature to validate link integrity
● Integrated termination resistors
● 1.8V, 2.8V or 3.3V compatible parallel inputs on Serializer
● Single power supply at 1.8V
● ISO 10605 and IEC 61000-4-2 ESD Compliant
● Temperature range −40℃ to +105℃
● Small serializer footprint (5mm x 5mm)
● No reference clock required on Deserializer
● Adaptive Receive Equalization
● EMI/EMC Mitigation
— DES Programmable Spread Spectrum (SSCG) outputs.
— DES Receiver staggered outputs
DS90UB913Q/DS90UB914Q應(yīng)用:
● Automotive Vision Systems
● Front camera for collision mitigation
● Rear view camera for backup protection
● Parking Assistance
圖1.DS90UB913Q/DS90UB914Q框圖
圖2.DS90UB913Q/DS90UB914Q應(yīng)用框圖
圖3.DS90UB913Q/DS90UB914Q典型應(yīng)用框圖
The DS90UB913Q/914Q evaluation boards consist of two sections. The first part of the board provides the point-to-point interface for transmitting parallel video data. The second part of the board allows bi-directional control communication of an I2C bus control of using a MCU/FPGA to programming a remote peripheral device via the Serializer.
圖4.DS90UB913Q/914Q評估板外形圖
The DS90UB913Q/914Q chipset supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream. The single differential pair (FPD-Link III) is well-suited for direct connections between an imager and Host Controller/Electronic Control Unit (ECU)/FPGA. The bidirectional control channel of the DS90UB913Q/914Q provides seamless communication between the ECU/FPGA and the imager module. Transmission of a full-duplex high-speed video data (10/12 bits of parallel data, two SYNC bits and PCLK), with transparent bi-directional control channel (I2C) over the same serial video link. Additionally, there are four unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer. This interface allows transparent (no dependency of video blanking interval) ,full-duplex communication over a single high-speed differential pair. The Serializer and Deserializer communicate data at PCLK clocks speeds ranging from 10 to 100 MHz and I2C bus rates up to 400 kbps at up to 25 meters cable length over -40 to +105 Deg C.
DS90UB913Q/914Q評估板主要特性:
On-board Rosenberger connectors for use with Leoni-Dacar cables (not included)
Optional single ended coaxial connectors to work with coaxial cables
Supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream
Requires only a single 5V supply
Power transfer over coax or power transfer over differential pair capability
Enables high-speed video data transmission, with integrated low latency bi-directional control, over a single twisted pair cable
Delivers 10/12 bits of parallel data, two SYNC bits and PCLK, with a bidirectional I2C bus control channel
Four additional unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer
Full-duplex communication and asymmetrical bi-directional control over a single high-speed differential pair, without video blanking intervals
Transmit data at PCLK clocks speeds, ranging from 10 to 100 MHz
I2C bus rates up to 400 kbps
圖5.DS90UB913Q EVK電路圖(1)
圖6.DS90UB913Q EVK電路圖(2)
圖7.DS90UB913Q EVK電路圖(3)
圖8.DS90UB914Q EVK電路圖(1)
圖9.DS90UB914Q EVK電路圖(2)
圖10.DS90UB914Q EVK電路圖(3)
圖11.DS90UB913Q評估板PCB布局圖
圖12.DS90UB914Q評估板PCB布局圖
圖13.汽車視頻控制框圖
詳情請見:
http://www.ti.com/lit/ds/snls420/snls420.pdf
和
http://www.ti.com/lit/ug/snlu110/snlu110.pdf
DS90UB913Q/DS90UB914Q主要特性:
● 10 MHz to 100 MHz input pixel clock support
● Single differential pair interconnect
● Programmable data payload:
— 10 bit payload up to 100Mhz
— 12 bit payload up to 75MHz
● Continuous Low Latency Bidirectional control interface channel with I2C support@400kHz
● 2:1 Multiplexer to choose between two input imagers
● Embedded clock with DC Balanced coding to support ACcoupled interconnects
● Capable of driving up to 25 meters shielded twisted-pair
● 4 dedicated General Purpose Input (GPI)/ Output (GPO)
● LOCK output reporting pin and AT-SPEED BIST diagnosis feature to validate link integrity
● Integrated termination resistors
● 1.8V, 2.8V or 3.3V compatible parallel inputs on Serializer
● Single power supply at 1.8V
● ISO 10605 and IEC 61000-4-2 ESD Compliant
● Temperature range −40℃ to +105℃
● Small serializer footprint (5mm x 5mm)
● No reference clock required on Deserializer
● Adaptive Receive Equalization
● EMI/EMC Mitigation
— DES Programmable Spread Spectrum (SSCG) outputs.
— DES Receiver staggered outputs
DS90UB913Q/DS90UB914Q應(yīng)用:
● Automotive Vision Systems
● Front camera for collision mitigation
● Rear view camera for backup protection
● Parking Assistance
圖1.DS90UB913Q/DS90UB914Q框圖
圖2.DS90UB913Q/DS90UB914Q應(yīng)用框圖
圖3.DS90UB913Q/DS90UB914Q典型應(yīng)用框圖
The DS90UB913Q/914Q evaluation boards consist of two sections. The first part of the board provides the point-to-point interface for transmitting parallel video data. The second part of the board allows bi-directional control communication of an I2C bus control of using a MCU/FPGA to programming a remote peripheral device via the Serializer.
圖4.DS90UB913Q/914Q評估板外形圖
The DS90UB913Q/914Q chipset supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream. The single differential pair (FPD-Link III) is well-suited for direct connections between an imager and Host Controller/Electronic Control Unit (ECU)/FPGA. The bidirectional control channel of the DS90UB913Q/914Q provides seamless communication between the ECU/FPGA and the imager module. Transmission of a full-duplex high-speed video data (10/12 bits of parallel data, two SYNC bits and PCLK), with transparent bi-directional control channel (I2C) over the same serial video link. Additionally, there are four unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer. This interface allows transparent (no dependency of video blanking interval) ,full-duplex communication over a single high-speed differential pair. The Serializer and Deserializer communicate data at PCLK clocks speeds ranging from 10 to 100 MHz and I2C bus rates up to 400 kbps at up to 25 meters cable length over -40 to +105 Deg C.
DS90UB913Q/914Q評估板主要特性:
On-board Rosenberger connectors for use with Leoni-Dacar cables (not included)
Optional single ended coaxial connectors to work with coaxial cables
Supports a variety of automotive mega-pixel camera systems over a two (2) wire serial stream
Requires only a single 5V supply
Power transfer over coax or power transfer over differential pair capability
Enables high-speed video data transmission, with integrated low latency bi-directional control, over a single twisted pair cable
Delivers 10/12 bits of parallel data, two SYNC bits and PCLK, with a bidirectional I2C bus control channel
Four additional unidirectional general purpose (GPI and GPO) signal lines from the Deserializer to the Serializer
Full-duplex communication and asymmetrical bi-directional control over a single high-speed differential pair, without video blanking intervals
Transmit data at PCLK clocks speeds, ranging from 10 to 100 MHz
I2C bus rates up to 400 kbps
圖5.DS90UB913Q EVK電路圖(1)
圖6.DS90UB913Q EVK電路圖(2)
圖7.DS90UB913Q EVK電路圖(3)
圖8.DS90UB914Q EVK電路圖(1)
圖9.DS90UB914Q EVK電路圖(2)
圖10.DS90UB914Q EVK電路圖(3)
圖11.DS90UB913Q評估板PCB布局圖
圖12.DS90UB914Q評估板PCB布局圖
圖13.汽車視頻控制框圖
詳情請見:
http://www.ti.com/lit/ds/snls420/snls420.pdf
和
http://www.ti.com/lit/ug/snlu110/snlu110.pdf
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