| 飛思卡爾Verilog編碼規(guī)范 | |
| 所屬分類：軟件 | |
| 上傳者：chenyy | |
| 文檔大小：344 K | |
| 標(biāo)簽： 開(kāi)發(fā)工具 | |
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| 文檔介紹：The Verilog HDL coding standards pertain to virtual component (VC) generation and deal with naming conventions, documentation of the code and the format, or style, of the code. Conformity to these standards simplifies reuse by describing insight that is absent from the code, making the code more readable and assuring compatibility with most tools. Any exceptions to the rules specified in this standard, except as noted,must be justified and documented.The standards promote reuse by ensuring a high adaptability among applications. The intent of this document is to ensure that the gate level implementation is identical to the HDL code as it is understood by astandard Verilog simulator. Partitioning can affect the ease that a model can be adapted to an application.The modeling practices section deals with structures that are typically difficult to address well in a synthesis environment and are needed to ensure pre- and post-synthesis consistency. | |
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