Freescale公司的MM912F634是S12 MagniV系列產(chǎn)品中一員,集成了link" href="http://m.jysgc.com/tags/繼電器" title="繼電器" target="_blank">繼電器驅(qū)動(dòng)以及LIN收發(fā)器.器件采用16位S12 CPU,具有32KB閃存和2.0KB RAM,背景調(diào)試(BDM)和調(diào)試模塊(DBG),帶SCI的LIN 2.1物理層接口,10位15通路的ADC,16位4通路的定時(shí)器模塊(TIM16B4C),8位2路PWM,六種高壓/叫醒輸入和三個(gè)低壓GPIO,主要用在汽車的門窗提升和座位控制以及LIN連接.本文介紹了MM912F634主要特性,方框圖,簡(jiǎn)化應(yīng)用電路以及評(píng)估板KIT912F634EVME主要特性,電路圖和材料清單(BOM).

The MM912_634 is part of the S12 MagniV portfolio which simplifies system design with easy-to-use, expertly integrated mixed-signal microcontrollers for automotive applications. This dual-die solution is built on proven S12 technology, enabling software and tool compatibility across the entire portfolio. The SMARTMOS-based analog die combines System Basis Chip (SBC) functionality and application specific functions, which include a Local Interconnect Network (LIN) transceiver, relay drivers, a DC motor current sense circuit, and a selection of high and low side digital I/O. Control of the analog die is via a new high performance internal Die to Die interface (D2D), which seamlessly integrates the analog IC registers into the MCU register map, to provide faster access than SPI based systems.

The MM912F634 is an integrated single package solution that integrates an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver.

MM912F634主要特性:

• 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM

• Background Debug (BDM) & Debug Module (DBG)

• Die to Die bus interface for transparent memory mapping

• On-chip oscillator & two independent watchdogs

• LIN 2.1 Physical Layer Interface with integrated SCI

• Six digital MCU GPIOs shared with SPI (PA5…0)

• 10-Bit, 15 Channel - Analog to Digital Converter (ADC)

• 16-Bit, 4 Channel - Timer Module (TIM16B4C)

• 8-Bit, 2 Channel - Pulse width modulation module (PWM)

• Six high voltage / Wake-up inputs (L5.0)

• Three low voltage GPIOs (PB2.0)

• Low Power Modes with cyclic sense & forced wake-up

• Current Sense Module with selectable gain

• Reverse Battery protected Voltage Sense Module

• Two protected low side outputs to drive inductive loads

• Two protected high side outputs

• Chip temperature sensor

• Hall sensor supply

• Integrated voltage regulator(s)

MM912F634目標(biāo)應(yīng)用:

Automotive:Doors, Window Lift and Seat Control

Connectivity :Local Interconnect Network (LIN)


圖1.MM912F634方框圖

圖2.MM912F634電源電路圖

圖3.MM912F634簡(jiǎn)化應(yīng)用電路圖

評(píng)估板KIT912F634EVME

Freescale Semiconductor’s KIT912F634EVME is a system solution which gives the user the capability to easily evaluate most of the features provided by the MM912F634 - Integrated Dual Low Side and Dual High Side Switch with Embedded MCU and LIN Transceiver for Relay Drivers. The 912F634 features 2 die in a single package. The 16-bit core and the analog die are connected by means of the Die to Die interface that provides direct address access to the registers on the analog die. The analog die contains HS and LS switches, as well as a PWM module, ADC module, timer module, SCI module, LIN physical interface, and other general registers. All external signals are accessible via header connectors, and most of the signals can also be checked via test points. The evaluation module board also includes the TBDML programming/debugging interface, so no external interface is needed. The board can be powered either from two 4.0 mm banana connectors or from the LIN connector. For quick familiarization with the device, a graphical user interface, based on FreeMASTER software, is provided together with the module. Thanks to the GUI, the user can easy evaluate the peripheral modules, or directly access the registers on the analog die.

評(píng)估板KIT912F634EVME主要特性:

•16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM

•Background Debug (BDM) & Debug Module (DBG)

•Die to Die bus interface for transparent memory mapping

•On-chip oscillator & two independent watchdogs

•LIN 2.1 Physical Layer Interface with integrated SCI

•Six digital MCU GPIOs shared with SPI (PA5…0)

•10-Bit, 15 Channel - Analog to Digital Converter (ADC)

•16-Bit, 4 Channel - Timer Module (TIM16B4C)

•8-Bit, 2 Channel - Pulse width modulation module (PWM)

•Six high voltage / Wake-up inputs (L5.0)

•Three low voltage GPIOs (PB2.0)

•Low Power Modes with cyclic sense & forced wake-up

•Current Sense Module with selectable gain

•Reverse Battery protected Voltage Sense Module

•Two protected low side outputs to drive inductive loads

•Two protected high side outputs

•Chip temperature sensor

•Hall sensor supply

•Integrated voltage regulator(s)

 
圖4.評(píng)估板KIT912F634EVME外形圖

圖5.評(píng)估板KIT912F634EVME電路圖(1)

圖6.評(píng)估板KIT912F634EVME電路圖(2)

評(píng)估板KIT912F634EVME材料清單(BOM):




圖7.評(píng)估板KIT912F634EVME元件布局圖
詳情請(qǐng)見:
http://cache.freescale.com/files/analog/doc/data_sheet/MM912F634.pdf?fpsp=1&WT_TYPE=Data%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
和
http://cache.freescale.com/files/analog/doc/user_guide/KT912F634UG.pdf?fpsp=1&WT_TYPE=Users%20Guides&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation