中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.229805 中文引用格式： 徐睿，王貽源. 基于HITOC DK與3DIC Integrity的3DIC芯片物理設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022，48(8)：55-59. 英文引用格式： Xu Rui，Wang Yiyuan. 3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology[J]. Application of Electronic Technique，2022，48(8)：55-59.
3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology
Xu Rui，Wang Yiyuan
ICLEAGUE，Shanghai 200000，China
Abstract： In this paper, Cadence 3DIC Integrity and ICLEAGUE HITOC Design Kit are used to implement the back-end of 3DIC logic stack logic chip. In the project, the separation, distribution, definition and other aspects of proto seeds(i.e., minimum distribution unit) in Cadence 3DIC Integrity were studied and optimized. In addition, the paper provided an algorithm of routing arrangement between the top-level power planning and Hybrid Bonding bump，which is optimized to obtain as many Hybrid Bonding bumps as possible and also keep the strength of the power network, thus increasing the number of ports between top die and bottom die. The final results of this paper show that compared with PPA(performance, power consumption and area)implemented by traditional 2D chips, the experiment has achieved 12% increase in frequency, 11.2% reduction in area and 2.5% reduction in power consumption.
Key words : 3DIC；logic stack logic；Hybrid Bonding；HITOC Design Kit；PPA
