中圖分類號(hào)：TN914 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234126
中文引用格式： 虞亞君，王小龍，邵春偉，等. 一種基于FPGA的eMMC壽命驗(yàn)證的方法[J]. 電子技術(shù)應(yīng)用，2024，50(2)：107-110.
英文引用格式： Yu Yajun，Wang Xiaolong，Shao Chunwei，et al. A method of eMMC lifetime verification based on FPGA[J]. Application of Electronic Technique，2024，50(2)：107-110.

A method of eMMC lifetime verification based on FPGA

Abstract： In order to meet the requirements of testing the long-term read and write performance of eMMC storage particles, an eMMC life verification design method is studied based on FPGA. Combined with eMMC working principle and high speed DDR（double rate）bus mode, the core components of verification system are designed in detail. FPGA（xc7a50tffgg484-1）is adopted as main control chip and four pieces of eMMC（FEMDRW064G-88A19）are selected as verification objects. The initial configuration method of eMMC is analyzed, and the module of open read and write is designed. With the control commands of the eMMC monitoring software, 180 000 times of loop read and write based on the blocks is completed. All the test results are passed, and the average read/write speed can reach 31 MB/s.

Key words : eMMC；lifetime verification；high speed DDR bus；FPGA