ADI公司的HSC-ADC-EVALCZ是采用Xilinx Virtex-4 FPGA的高速ADC評估平臺,能從ADI高速ADC評估板中捕獲數字數據.平臺通過USB端口連接到PC,采用VisualAnalog®快速評估高速ADC的性能,與之配套的有ADI ADC高速評估板,信號源和時鐘源.平臺具有64 kB FIFO深度, 644 MSPS SDR 和800 MSPS DDR并行輸入,支持1.8 V, 2.5 V和3.3 V CMOS與LVDS接口,支持高達18位的多個ADC通路.本文介紹了HSC-ADC-EVALCZ評估平臺產品亮點和主要特性,功能框圖以及電路圖,材料清單與PCB元件布局圖.
The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
HSC-ADC-EVALCZ評估平臺產品亮點:
1. Easy to Set Up. Connect the included power supply along with the CLK and AIN signal sources to the two evaluation boards. Then connect to the PC via the USB port and evaluate the performance instantly.
2. USB Port Connection to PC. PC interface is via a USB 2.0 connection (1.1 compatible) to the PC. A USB cable is provided in the kit.
3. 64 kB FIFO. The on-board FPGA contains an integrated FIFO to store data captured from the ADC for subsequent processing.
4. Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on Each Channel. Multichannel ADCs with encode rates up to 644 MSPS SDR and 800 MSPS DDR can be used with the ADC capture board.
5. Supports ADCs with Serial Port Interface or SPI. Some ADCs include a feature set that can be changed via the SPI. The ADC capture board supports these SPI-driven features through the existing USB connection to the computer without additional cabling needed.
6. VisualAnalog™. VisualAnalog supports the HSC-ADC-EVALC hardware platform as well as enabling virtual ADC evaluation using ADIsimADC™, Analog Devices proprietary behavioral modeling technology. This allows rapid compari-son between multiple ADCs, with or without hardware evaluation boards.
HSC-ADC-EVALCZ評估平臺主要特性:
Xilinx Virtex-4 FPGA-based buffer memory board
Used for capturing digital data from high speed ADC evaluation boards to simplify evaluation
64 kB FIFO depth
Parallel input at 644 MSPS SDR and 800 MSPS DDR
Supports 1.8 V, 2.5 V, and 3.3 V CMOS and LVDS interfaces
Supports multiple ADC channels up to 18 bits
Measures performance with VisualAnalog
Real-time FFT and time domain analysis
Analyzes SNR, SINAD, SFDR, and harmonics
Simple USB port interface (2.0)
Supports ADCs with serial port interfaces (SPI)
FPGA reconfigurable via JTAG, on-board EPROM, or USB
On-board regulator circuit speeds setup
5 V, 3 A switching power supply included
Compatible with Windows 98 (2nd edition), Windows 2000, Windows ME, and Windows XP
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
Low jitter clock source
High speed ADC evaluation board and ADC data sheet
PC running Windows 98 (2nd edition), Windows 2000, Windows ME, or Windows XP
Latest version of VisualAnalog
USB 2.0 port recommended (USB 1.1 compatible)
圖1.HSC-ADC-EVALCZ評估平臺功能框圖
圖2.HSC-ADC-EVALCZ評估平臺外形和元件分布圖
圖3.HSC-ADC-EVALCZ評估平臺電路圖(1)
圖4.HSC-ADC-EVALCZ評估平臺電路圖(2)
圖5.HSC-ADC-EVALCZ評估平臺電路圖(3)
圖6.HSC-ADC-EVALCZ評估平臺電路圖(4)
圖7.HSC-ADC-EVALCZ評估平臺電路圖(5)
圖8.HSC-ADC-EVALCZ評估平臺電路圖(6)
圖9.HSC-ADC-EVALCZ評估平臺電路圖(7)
圖10.HSC-ADC-EVALCZ評估平臺電路圖(8)
圖11.HSC-ADC-EVALCZ評估平臺電路圖(9)
圖12.HSC-ADC-EVALCZ評估平臺電路圖(10)
圖13.HSC-ADC-EVALCZ評估平臺電路圖(11)
圖14.HSC-ADC-EVALCZ評估平臺電路圖(12)
圖15.HSC-ADC-EVALCZ評估平臺電路圖(13)
HSC-ADC-EVALCZ評估平臺材料清單:
圖16.HSC-ADC-EVALCZ評估平臺PCB元件布局圖(頂層)
圖17.HSC-ADC-EVALCZ評估平臺PCB元件布局圖(底層)
詳情請見:
http://www.analog.com/static/imported-files/eval_boards/265181843HSC_ADC_EVALC.pdf
和
http://www.analog.com/static/imported-files/application_notes/57206466474685142207552745732150239440755569051663372515871138132239AN_835_0.pdf