Freescale公司的i.MX 6SoloLite是用于消費類電子的多媒體應用處理器,采用單個ARM® Cortex®-A9 MPCore™多核處理器,工作頻率高達1GHz,集成了2D圖像處理器和電源管理,提供32位DDR3-800存儲器接口以及連接外設的接口如WLAN,藍牙,GPS,硬盤驅動,顯示器和照相機傳感器等.主要應用在汽車,娛樂,PND,消費電子,電子閱讀器,多媒體手機,游戲機和醫療電子于工業.本文介紹了i.MX 6SoloLite 處理器主要特性,框圖, 汽車娛樂系統SABRE平臺主要特性,開發板框圖與主要元件和電路圖.

The i.MX 6SoloLite processor represents Freescale’s latest achievement in integrated multimedia applications processors, which are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption.

The processor features Freescale’s advanced implementation of the a single ARM® Cortex®-A9 MPCore™ multicore processor, which operates at speeds up to 1 GHz. It includes 2D graphics processor and integrated power management. The processor provides a 32-bit DDR3-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, displays,and camera sensors.

i.MX 6SoloLite 應用處理器目標應用:

Automotive
Infotainment  
Consumer
Portable Navigation Devices  
E-Readers  
Media Phones  
Mobile Consumer Electronics
Remote Controls  
Gaming and Pachinko Machines
Wireless Insulin Pump  
Continuous Glucose Monitor  
Industrial
HVAC Building and Control Systems
Fire alarms
Smart Grid and Smart Metering  
Color and monochrome eReaders
Entry level tablets
Barcode scanners

i.MX 6SoloLite 處理器主要特性:

• Applications processor—The processor enhances the capabilities of high-tier portable applications by fulfilling the ever increasing MIPS needs of operating systems and games. Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks, such as audio decode.

• Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processor supports many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR Flash, PSRAM, cellular RAM, and managed NAND, including eMMC up to rev 4.4/4.41.

• Smart speed technology—The processor has power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product, requiring levels of power far lower than industry expectations.

• Dynamic voltage and frequency scaling—The processor improves the power efficiency of devices by scaling the voltage and frequency to optimize performance.

• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, and a programmable smart DMA (SDMA) controller.

• Powerful graphics acceleration—Each processor provides three independent, integrated graphics processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.

• Interface flexibility—The processor supports connections to a variety of interfaces: LCD controller, CMOS sensor interface (parallel), high-speed USB on-the-go with PHY, high-speed USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100 Mbps Ethernet controller, and a variety of other popular interfaces (such as UART, I2C, and I2S serial audio).

• Electronic Paper Display Controller—The processor integrates EPD controller that supports E-INK color and monochrome with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096 resolution at 20 Hz refresh and 5-bit grayscale (32-levels per color channel).

• Advanced security—The processor delivers hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. The security features are discussed in detail in the i.MX 6SoloLite security reference manual (IMX6SLSRM). Contact your local Freescale representative for more information.

• Integrated power management—The processor integrates linear regulators and generate internally all the voltage levels for different domains. This significantly simplifies system power management structure.

• GPIO with interrupt capabilities—The new GPIO pad design supports configurable dual voltage rails at 1.8V and 3.3V supplies. The pad is configurable to interface at either voltage level.

The i.MX 6SoloLite processor is based on ARM Cortex-A9 MPCore multicore processor, which has the following features:

• ARM Cortex-A9 MPCore CPU processor (with TrustZone)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) co-processor
The ARM Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 256 KB unified I/D L2 cache
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache)
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
• External memory interfaces:
— 16-bit, and 32-bit DDR3-800, and LPDDR2-800 channels
— 16/32-bit NOR Flash.
— 16/32-bit PSRAM, Cellular RAM (32 bits or less)
Each i.MX 6SoloLite processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):
• Displays—Total three interfaces are available.
— LCD, 24bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz)
— EPDC, color, and monochrome E-INK, up to 1650x2332 resolution and 5-bit grayscale
• Camera sensors:
— Parallel Camera port (up to 16 bit)
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)
• USB:
— Two High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
— One USB 2.0 (480 Mbps) hosts:
– One HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy
• Miscellaneous IPs and interfaces:
— Three I2S/SSI/AC97 supported
— Five UARTs, up to 4.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical.
— Four eCSPI (Enhanced CSPI)
— Three I2C, supporting 400 kbps
— Ethernet Controller, 10/100 Mbps
— Four Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Sony Philips Digital Interface (SPDIF), Rx and Tx
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
The i.MX 6SoloLite processor integrates advanced power management unit and controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
• Support DVFS techniques for low power modes
• Use Software State Retention and Power Gating for ARM and MPE
• Support various levels of system power modes
• Use flexible clock gating control scheme
The i.MX 6SoloLite processor uses dedicated HW accelerators to meet the targeted multimedia performance. The use of HW accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6SoloLite processor incorporates the following hardware accelerators:
• GPU2Dv2—2D Graphics Processing Unit (BitBlt).
• GPUVG—OpenVG 1.1 Graphics Processing Unit.
• PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to support the EPD display applications.
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features.
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock.
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization


圖1. i.MX 6SoloLite 處理器框圖

汽車娛樂系統SABRE平臺

The SABRE platform for Automotive Infotainment offers a solid foundation for next-generation converged telematics and infotainment platform designs. The i.MX 6 series of applications processors represents our scalable family of products powered by single-, dual- and quad-core implementations of the ARM® Cortex™-A9 core for the automotive market. With multicore processing speeds of up to 1 GHz as well as a high level of integration, the SABRE for Automotive Infotainment enables customers to recreate today’s consumer user experiences in the car.

汽車娛樂系統SABRE平臺主要特性:

The following features are available with the SABRE for Automotive Infotainment CPU card:
1 GHz i.MX 6Q processor or 800 MHz i.MX 6DL processor
i.MX 6Q: 4 x 4 Gb DDR3 at 533 MHz (DDR-1066)
i.MX 6DL: 4 x 4 Gb DDR3 at 400 MHz (DDR-800)
32 MB 16-bit parallel NOR flash
NAND flash socket
LVDS output
RGB parallel output
MLB150 INIC connector
SD card slot
High-Speed USB OTG interface
SATA interface (i.MX 6Q only)
Ethernet interface
JTAG and UART interfaces
Capable of running stand-alone on common 5 V DC power supply
281 card-edge fingers for base board connection or interface to user’s system


圖2. 汽車娛樂系統SABRE平臺外形圖

圖3.汽車娛樂系統SABRE平臺MCIMX6SLEVK板框圖

圖4. SABRE平臺MCIMX6SLEVK板電路圖(1)

圖5. SABRE平臺MCIMX6SLEVK板電路圖(2)

圖6. SABRE平臺MCIMX6SLEVK板電路圖(3)

圖7. SABRE平臺MCIMX6SLEVK板電路圖(4)

圖8. SABRE平臺MCIMX6SLEVK板電路圖(5)

圖9. SABRE平臺MCIMX6SLEVK板電路圖(6)

圖10. SABRE平臺MCIMX6SLEVK板電路圖(7)

圖11. SABRE平臺MCIMX6SLEVK板電路圖(8)


圖12. SABRE平臺MCIMX6SLEVK板電路圖(9)

圖13. SABRE平臺MCIMX6SLEVK板電路圖(10)

圖14. SABRE平臺MCIMX6SLEVK板電路圖(11)

圖15. SABRE平臺MCIMX6SLEVK板電路圖(12)

圖16. SABRE平臺MCIMX6SLEVK板電路圖(13)

圖173. SABRE平臺MCIMX6SLEVK板電路圖(14)

詳情請見:
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SLCEC.pdf?pspll=1
和
http://cache.freescale.com/files/product/hardware_tools/MCIMX6SLEVK.pdf?fr=g