中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.209804
中文引用格式： 林楷智，宗艷艷，孫龍，等. 12 V電源平面對DDR4信號的影響[J].電子技術應用，2020，46(8)：68-71，76.
英文引用格式： Lin Kaizhi，Zong Yanyan，Sun Long，et al. Analysis of the effect of 12 V power plane on DDR4 signal[J]. Application of Electronic Technique，2020，46(8)：68-71，76.

Analysis of the effect of 12 V power plane on DDR4 signal

Abstract： With the rapid development of the Internet, the 5G era has arrived and the data transmission rate is getting higher, which is a new challenge to the server research. The memory development has upgraded from DDR3 to DDR4, its operating voltage has reduced to 1.2 V, and the rising edge of the DDR4 signal has dropped to 100 picoseconds. In order to ensure the transmission rate and accuracy of the signal, the crosstalk on the DDR4 transmission line cannot be ignored. This paper adopts the DDR4 transmission line on the motherboard of the server project. Firstly, different motherboard stack models have been designed, and different stackups are used to change the remote reference layer of DDR4. Then the experiment result under different stackups through simulation by Sigrity tools and actual testing has been analyzed. The result shows that the far reference to the 12 V power plane will cause crosstalk of more than tens of millivolts to the DDR4 signal. After adding the ground plane shield between the 12 V power layer and the signal layer, the crosstalk voltage is significantly reduced.

Key words : DDR4；far reference plane；simulation analysis；stackup；Sigrity