基于FPGA的高精度鑒相器實(shí)現(xiàn)
2020年電子技術(shù)應(yīng)用第10期
董淑豪1，吳東岷2
1.中國(guó)科學(xué)技術(shù)大學(xué) 微電子學(xué)院，安徽 合肥230026； 2.中國(guó)科學(xué)院蘇州納米技術(shù)與納米仿生研究所，江蘇 蘇州215000
摘要： 基于模擬電路的鑒相器雖然響應(yīng)速度快，但是很難達(dá)到較高的精度，并且開(kāi)發(fā)周期長(zhǎng)不易優(yōu)化。為了可以實(shí)時(shí)檢測(cè)MEMS器件諧振時(shí)微小的相位變化，提出一種基于FPGA的高精度鑒相器。該鑒相器主要是由數(shù)字混頻器、FIR數(shù)字濾波器、DDS信號(hào)發(fā)生器以及模數(shù)轉(zhuǎn)換電路組成。鑒相方法是通過(guò)將被測(cè)信號(hào)與一同頻、相位可調(diào)、且初始相位為90°的參考信號(hào)混頻，并通過(guò)高階FIR濾波器提取與相位有關(guān)的差頻信號(hào)，調(diào)節(jié)參考信號(hào)相位使得此差頻信號(hào)趨近于0，則此參考信號(hào)的相位調(diào)節(jié)量即為被測(cè)信號(hào)的相位。鑒相器的時(shí)鐘頻率為100 MHz，鑒相精度可以達(dá)到0.000 1°。工作頻率靈活可調(diào)，并且應(yīng)用于鎖相環(huán)中時(shí)，可以很方便地與MEMS器件的驅(qū)動(dòng)電路兼容。
中圖分類(lèi)號(hào)： TN763.3
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.200377
中文引用格式： 董淑豪，吳東岷. 基于FPGA的高精度鑒相器實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用，2020，46(10)：57-60，78.
英文引用格式： Dong Shuhao，Wu Dongmin. Realization of high precision phase detector based on FPGA[J]. Application of Electronic Technique，2020，46(10)：57-60，78.
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.200377
中文引用格式： 董淑豪，吳東岷. 基于FPGA的高精度鑒相器實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用，2020，46(10)：57-60，78.
英文引用格式： Dong Shuhao，Wu Dongmin. Realization of high precision phase detector based on FPGA[J]. Application of Electronic Technique，2020，46(10)：57-60，78.
Realization of high precision phase detector based on FPGA
Dong Shuhao1，Wu Dongmin2
1.School of Microelectronics，University of Science and Technology of China，Hefei 230026，China； 2.Suzhou Institue of Nano-Tech and Nano-Bionics，Suzhou 215000，China
Abstract： Although the response speed of the phase detector based on analog circuit is fast, it is difficult to achieve high precision, and the development cycle is long and difficult to optimize. In order to detect the tiny phase change of micro-electro-mechanical system(MEMS) devices in real time, a high-precision phase detector based on field programmable gate array(FPGA) is proposed. The phase detector is mainly composed of digital mixer, finite impulse response(FIR) digital filter, direct digital synthesis(DDS) signal generator and analog digital converter conversion circuit. The phase detection method is to mix the measured signal with the reference signal with the same frequency, adjustable phase and initial phase of 90°, and extract the phase related difference frequency signal through high-order FIR filter, adjust the reference signal phase to make the difference frequency signal close to 0, then the phase adjustment amount of the reference signal is the phase of the measured signal. The clock frequency of the phase detector is 100 MHz, and the phase accuracy can reach 0.000 1°. The working frequency is flexible and adjustable. When it is used in PLL, it can be easily compatible with the driving circuit of MEMS devices.
Key words : FPGA；FIR；phase detector；DDS；MEMS
0 引言
微機(jī)電系統(tǒng)(Micro-Electro-Mechanical System，MEMS)，體積小、功耗低、諧振頻率高、光學(xué)特性好[1]，在醫(yī)療、軍事、科研等領(lǐng)域得到廣泛應(yīng)用。在MEMS微振鏡的同步控制過(guò)程中，傳統(tǒng)的模擬鑒相器很難達(dá)到較高精度，并且模擬鑒相器開(kāi)發(fā)周期長(zhǎng)，不易優(yōu)化。基于現(xiàn)場(chǎng)可編程門(mén)陣列(Field Programmable Gate Array，FPGA)的數(shù)字鑒相器可以大大提高鑒相精度[2]，并且靈活可調(diào)，方便實(shí)現(xiàn)MEMS微鏡的同步控制。
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作者信息:
董淑豪1，吳東岷2
(1.中國(guó)科學(xué)技術(shù)大學(xué) 微電子學(xué)院，安徽 合肥230026；
2.中國(guó)科學(xué)院蘇州納米技術(shù)與納米仿生研究所，江蘇 蘇州215000)
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