中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.201109 中文引用格式： 吳霞，鮑言鋒，鄧婉玲，等. 基于0.35 ?滋m CMOS工藝的高溫高壓LDO芯片設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2021，47(12)：120-125. 英文引用格式： Wu Xia，Bao Yanfeng，Deng Wanling，et al. Design of high temperature and high voltage LDO using 0.35 ?滋m CMOS process[J]. Application of Electronic Technique，2021，47(12)：120-125.
Design of high temperature and high voltage LDO using 0.35 ?滋m CMOS process
Wu Xia，Bao Yanfeng，Deng Wanling，Huang Junkai
College of Information Science and Technology，Jinan University，Guangzhou 510632，China
Abstract： In this paper, based on X-FAB xa 0.35 μm CMOS process, a cascode current mirror and high voltage MOS transistors are used to design a high temperature and high voltage reference circuit with high power supply rejection ratio without additional bias circuit module, and thus, a stable 0.9 V reference voltage can be obtained when the input voltage is in the range of 5.5 V~30 V and the operating temperature is in the range of -55 ℃~175 ℃. Then, according to the principle of dynamic zero compensation, a new dynamic zero compensation circuit is designed to make the system to maintain stability in the full load voltage range. At the same time, with the design of other circuit modules such as over-temperature protection, over-voltage protection, over-current protection and logic control circuit modules, a low-dropout linear regulator(LDO) chip with high temperature and high voltage is finally designed, the area of which is 2.822 3 mm2.
Key words : LDO；CMOS；high temperature and voltage；0.35 μm process
