中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.250803 中文引用格式： 姜姝，李嶧，陳俊杰. Voltus Insight AI 在高性能CPU核物理實現(xiàn)上的全流程應(yīng)用[J]. 電子技術(shù)應(yīng)用，2025，51(8)：16-21. 英文引用格式： Jiang Shu，Li Yi，Chen Junjie. Application of Voltus Insight AI in physical implementation of high-performance CPU cores[J]. Application of Electronic Technique，2025，51(8)：16-21.
Application of Voltus Insight AI in physical implementation of high-performance CPU cores
Abstract： With the evolution of high-performance computing chip design toward advanced process nodes, the exponential growth in chip integration has led transistor density to surpass hundreds of millions of gates per square millimeter. This has resulted in the continuous narrowing of metal line widths in Power Distribution Networks (PDNs), a nonlinear rise in via resistance, and synchronized switching behavior of high-density logic units under GHz-level clock frequencies, significantly exacerbating IR Drop risks. Leveraging the Cadence Voltus Insight AI feature, this paper proposes a comprehensive voltage drop optimization solution for the physical implementation of high-performance CPU cores. By integrating AI-driven IR-Aware placement, reinforce_pg, and Watch Box repair technologies, the solution dynamically predicts current distribution hotspots in PDNs, optimizes the placement of high-power logic units, and enables proactive prevention and efficient mitigation of IR hotspots. Experimental results demonstrate that, under identical conditions, the approach not only saves time and improves efficiency but also elevates the IR Drop repair rate from 66% to 96%, while avoiding degradation in timing performance and Design Rule Check (DRC).
Key words : chip design；Insight AI；IR-Aware；IR Drop fixing
引言
隨著高性能計算芯片的集成度呈現(xiàn)指數(shù)級增長，晶體管密度已突破每平方毫米數(shù)億門級，為算力提升開辟了全新維度。然而，這種物理尺度的極致壓縮與性能的追求，給芯片設(shè)計帶來了新的挑戰(zhàn)。其中，電壓降（IR Drop）問題尤為突出——電源分配網(wǎng)絡(luò)（Power Distribution Network, PDN）的金屬線寬持續(xù)收窄，通孔電阻隨高密度互連呈非線性攀升，疊加高密度邏輯單元在吉赫茲級時鐘頻率下的同步翻轉(zhuǎn)行為，導(dǎo)致局部電流密度激增，顯著加劇了IR Drop風(fēng)險。當電源電壓無法滿足晶體管閾值要求時，輕則引發(fā)時序偏差與性能降級，重則導(dǎo)致功能失效，成為制約先進工藝芯片可靠性與能效的核心瓶頸 [1-4]。本文基于Cadence實現(xiàn)工具Innovus和 Voltus Insight AI feature，提出了一種針對高性能CPU核的物理實現(xiàn)的全流程電壓降優(yōu)化方案，通過整合AI驅(qū)動的IR感知布局（IR-Aware Placement）、電源網(wǎng)絡(luò)加強（reinforce_pg）及Watch Box修復(fù)技術(shù)，動態(tài)預(yù)測電源網(wǎng)格的電流分布熱點，對高功耗邏輯單元進行擺放優(yōu)化，實現(xiàn)IR 熱點區(qū)域的提前預(yù)防和高效修復(fù)。
