簡(jiǎn)單改變FPGA計(jì)數(shù)器規(guī)格使作為DAC功能PWM計(jì)數(shù)器的紋波降低。
當(dāng)需要一些模擬輸出和系統(tǒng)中有FPGA時(shí)，很可能選擇使用如圖1的PWM模塊和簡(jiǎn)單低通濾波器。FPGA的輸出是固定頻率、計(jì)數(shù)器和數(shù)字比較器使占空比可變的典型波形（表1）。
假設(shè)高信號(hào)使能，計(jì)數(shù)器每個(gè)時(shí)鐘周期進(jìn)行計(jì)數(shù)，PWM輸出的頻率為時(shí)鐘頻率的2次冪分頻。通過(guò)連接前置比例器，使用使能來(lái)降低輸出頻率。由于輸出頻率固定，濾波器容易計(jì)算。已知占空比50%時(shí)，出現(xiàn)最壞的紋波。最大紋波和上升時(shí)間的限制結(jié)合決定濾波器類(lèi)型和RC（電阻/電容）值。
對(duì)表1中編碼進(jìn)行非小改動(dòng)，能夠改進(jìn)PWM電路的性能。但在原先系統(tǒng)中，最大紋波電流發(fā)生在50%占空比時(shí)，最小紋波電流發(fā)生在最小占空比時(shí)，改進(jìn)的版本顯示最大紋波等于標(biāo)準(zhǔn)版的最小值。關(guān)鍵是產(chǎn)生最高頻率的可能性，還能保持平均的占空比常數(shù)。輸出脈沖頻率越高，濾波器性能越好。
從左到右交換所有位來(lái)修改由重編二進(jìn)制比較器組成表1。MSB（最高有效位）變成LSB（最低有效位），LSB變成MSB，等等（表2）。只需重編位，而不需額外寄存器或邏輯單元。
表3顯示了4位PWM發(fā)出的脈沖序列。表3中，可以看到50%占空比時(shí)（第二列，值為8），頻率最大，為時(shí)鐘頻率的２分頻。在第一個(gè)紋波出現(xiàn)點(diǎn)（第二列，值為1），傳統(tǒng)PWM系統(tǒng)中有同樣的紋波，也就是說(shuō)，脈沖序列是相同的。
英文原文：
Swapping bits improves performance of FPGA-PWM counter
A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC.
Stefaan Vanheesbeke, Ledegem, Belgium; Edited by Charles H Small and Fran Granville -- EDN, 9/13/2007
When you need some analog outputs and you have an FPGA in your system, you probably choose to use a PWM module and a simple lowpass filter such as those in Figure 1. The output of the FPGA is typically a waveform with a fixed-frequency, variable-duty cycle, which a counter and a digital comparator generate (Listing 1).
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits. You can use Enable to lower the output frequency by connecting it to a prescaler. Because the output frequency is fixed, the filter is easy to calculate, because you know that the worst-case ripple happens at a duty cycle of 50%. The combination of the desired maximum ripple and settling time determines the filter type and RC (resistance/capacitance) values.
With a small change to the code in Listing 1, you can improve the performance of the PWM circuit. Whereas in the original system, the maximum ripple currents occur at a duty cycle of 50% and the minimum ripple currents occur at the minimum duty cycle, the improved version shows a maximum ripple equal to the minimum of the standard version. The trick is to generate the highest frequency possible but keep the average duty cycle constant. The higher the frequency of the pulses on the output, the better the filter does its job.
The modification to Listing 1 consists of rewiring the binary comparator with all the bits swapped from left to right. The MSB (most significant bit) becomes the LSB (least significant bit), the LSB becomes the MSB, and so on (Listing 2). You do only a rewiring requiring no extra registers or logic.
Listing 3 shows the pulse trains that a 4-bit PWM emits. In Listing 3, you see that at 50% duty cycle (Value=8, second column), the frequency is maximum and equal to the clock frequency divided by two. At the first point at which some ripple shows up (Value=1, second column), there is exactly the same ripple as in the conventional PWM system—that is, the pulse train is the same.
英文原文地址：http://www.edn.com/article/CA6475009.html