中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.219803
中文引用格式： 程濤. 基于Palladium AVIP的SoC驗證方案[J].電子技術(shù)應(yīng)用，2021，47(8)：52-55.
英文引用格式： Cheng Tao. SoC verification solution based on Palladium AVIP[J]. Application of Electronic Technique，2021，47(8)：52-55.

SoC verification solution based on Palladium AVIP

Abstract： Due to the increasing scale of the chip, the EDA simulation speed has been difficult to meet the schedule requirements in some large scene cases. At the same time, the capacity of the FPGA prototype verification platform is limited, and some clock trees need to be modified and are not suitable for power/performance evaluation. Simulation acceleration and power analysis and performance evaluation based on Emulator platform have become a trend. Based on the emulator AVIP to simulate or monitor related bus transaction can be used to do the related work of function/power/performance which can greatly accelerated the process of chip development. The test cases developed based on MIPI AVIP for verifying MIPI or using MIPI to verify the internal image processing module achieves dozens of times of acceleration ratio and greatly improves the simulation speed. As well as using AVIP to simulate and monitor the behavior of related modules，can get the netlist power data and performance data. It has made an important contribution to the functional verification and power/performance optimization of the chip.

Key words : Emulator；AVIP；simulation acceleration；power analysis；performance estimation